Engineering Surface Morphology

The silicon (111) and (001) surfaces have wide technological importance. Control of the morphologies of these surfaces at the atomic level is vital for such applications as layer-by-layer growth of epitaxial overlayers or assembly of nano-scale devices. By creating large areas with no or widely spaced atomic steps on patterned silicon surfaces by ultra-high vacuum (UHV) annealing, surface structures generated by surface premelting can be analyzed by simple quenching. The early roughness variation as a function of temperature and the morphologies that develop close to the boundaries of etched craters on Si(111) during UHV processing were also studied. Two applications using the substrates processed by UHV annealing were described. First, MOS capacitors were built on three types of Si(111) surfaces viz. atomically flat surfaces, stepped surfaces cleaned in UHV, and normal, RCA cleaned wafer surfaces. As expected, the smoother the Si substrate, the lower is the leakage current. In another application, Si(111) substrates with regular arrays of atomic steps were used to induce azimuthal alignment of crystals in thin polycrystalline pentacene films.

Autorentext

Valerian Ignatescu works as process engineer at Intel since July 2007. He attended "Gh. Asachi" Technical University, and "Al. I. Cuza" University, Iasi, Romania where he acquired BS degrees in Mechanical Engineering and Applied Physics respectively. He also received a MS in Plasma Physics (1999) and a PhD in Physics (2004) from "Al. I. Cuza University". In 2007 he completed a PhD program in Materials Science and Engineering at Conell University, Ithaca, NY.