Error Control for Network-on-Chip Links

This book reviews the state of the art in error control for Network on Chip (NOC) links. It details key issues in NOC error control faced by circuit and system designers as well as practical error control techniques to minimize the impact of these errors.

This book provides readers with a comprehensive review of the state of the art in error control for Network on Chip (NOC) links. Coverage includes detailed description of key issues in NOC error control faced by circuit and system designers, as well as practical error control techniques to minimize the impact of these errors on system performance.

Provides a detailed background on the state of error control methods for on-chip interconnects, including Error Control Coding, Double Sampling, and On-Line Testing Describes the use of more complex concatenated codes such as Hamming Product Codes with Type-II HARQ, while emphasizing integration techniques for on-chip interconnect links Presents techniques for managing intermittent and permanent errors using a non-interrupting in-line test method with spare wire replacement Examines energy-efficient techniques for integrating multiple error control methods in on-chip interconnects

Klappentext

As technology scales into nanoscale regime, it is impossible to guarantee the perfect hardware design. Moreover, if the requirement of 100% correctness in hardware can be relaxed, the cost of manufacturing, verification, and testing will be significantly reduced. Many approaches have been proposed to address the reliability problem of on-chip communications. This book focuses on the use of error control codes (ECCs) to improve on-chip interconnect reliability. Coverage includes detailed description of key issues in NOC error control faced by circuit and system designers, as well as practical error control techniques to minimize the impact of these errors on system performance.

• Provides a detailed background on the state of error control methods for on-chip interconnects;
• Describes the use of more complex concatenated codes such as Hamming Product Codes with Type-II HARQ, while emphasizing integration techniques for on-chip interconnect links;
• Examines energy-efficient techniques for integrating multiple error control methods in on-chip interconnects;

• Introduces various design techniques to tradeoff the reliability and energy consumption of on-chip interconnects, including implementation of low link swing voltage and dynamic voltage scaling with error control codes, combination of Hamming product codes with type-II hybrid ARQ, and configurable error control codes implementation.

  Inhalt

Introduction.- Solutions to Improve the Reliability of On-Chip Interconnects.- Networks-on-Chip (NoC).- Error Control Coding for On-Chip Interconnects.- Energy Efficient Error Control Implementation.- Combining Error Control Codes with Crosstalk Reduction.