Fault Tolerance through Self-configuration in Nanoscale Processors

This work is a contribution at the architectural level to the improvement of fault tolerance in massively defective multicore chips fabricated using nanometer transistors. The main idea of this work is that a chip should be organized in a replicated architecture and become as autonomous as possible to increase its resilience against both permanent defects and transient faults occurring at runtime. Therefore, we introduce a new chip self-configuration methodology, which allows detecting and isolating the defective cores, deactivating the isolated cores, configuring the communications between the cores and managing the allocation and execution of tasks. The efficiency of the proposed methods is studied as a function of the fraction of defective cores, the fraction of defective interconnects and the soft error rate.

Autorentext

Piotr Zajac, PhD: Studied Electronics at the Technical University of Lodz, Poland. Received his PhD in 2008 from the National Institute of Applied Sciences of Toulouse, France. Lecturer at the Technical University of Lodz. Research interests: processor architecture and fault tolerance in multi-core systems.