FPGA Based 32-bit RISC Communication Processor Design

The proposed FPGA based 64-bit RISC Communication Processor (RCP) design for developing the processor with 32 operations using pipeline feature is an efficient technique in which basic processor operations like arithmetic and logical unit, shifting unit, comparator unit based. And a special communication unit which has signal generation and transmission operations and application unit which consist of traffic light, digital clock generation and LFSR (linear feedback Shift Register) operations are been incorporated into the design of RCP. The RCP design is implemented using Virtex 7 using Verilog HDL and is compared with other FPGA members like Spartan 3E and Spartan 3A DSP.

Autorentext

Dr. Joseph Anthony Prathap was born in 1981 in Puducherry. He has obtained B.E [Electronics and Communication] and M. Tech [VLSI Design] degrees in 2003 and 2007 respectively, and the Ph.D. in FPGA based Power Converters in 2017 from Annamalai University. He is currently an Associate Professor, E.C.E, Vardhaman College of Engineering, Hyderabad.