FPGA Based Self-test Systems

With I/O speeds increasing rapidly, there is a need to find efficient ways of designing hardware circuits to characterize and test these high speed interfaces. Traditionally, Bit Error Rate (BER) is evaluated using software simulations and stand-alone BER test products, which are either time-consuming or expensive. In this book, I demonstrate the design and implementation of a self-contained FPGA-based systems that can be used to test these interconnects. We present a user-configurable system that is capable of generating and evaluating the ITU-T recommended test patterns simultaneously over three channels with data rates of up to 3 Gb/s per channel. This includes the design of high-speed random pattern generator designs in Verilog and C-code for the integrated Power-PC processor to handle control of the user interface. The book also includes schematics of the current system and board design ideas for the readers to design their own systems.

Autorentext

Manav Shah is a hardware engineer with over 10 years of experience in designing ASIC and FGPA-based systems. He has worked with ISRO(Indian Space Research Organization), IBM Corp, and is currently employed as an ASIC designer at Qualcomm Inc. He holds an MS degree in Electrical Engineering and is currently pursuing an MS in Wireless health devices