FPGA Implementation of MIL-STD-1553B Bus Protocol

Modern day avionics and satellite communication systems communicate with each other using MIL-STD- 1553B bus protocol. This book aim to provide an intensive study for the software and hardware level implementation of MIL-STD-1553B bus protocol on FPGA board using a new methodology of digital phase lock loop (DPLL). The book describes the basics of bus protocol, modular level implementation of different units of protocol and software & hardware implementation issues and their solutions. ISE Xilinx Spartan 3 FPGA kit is used for the execution of different modules of protocol like UART, Bus Controller, Manchester encoder/decoder and DPLL. DPLL is used for data clock recovery from encoded Manchester data of the channel at receiver end, instead of implementing common practice of initiating a separate clock for encoded Manchester data processing. Usage of DPLL, resolves the synchronization issues, a major concern in high data rate embedded systems and increases the integrity and reliability of the system. The actual implementation of different transactions of bus i.e. BC to RT and RT to RT is discussed in detailed.

Autorentext

Jawad Yousaf,BSc (Cum Laude): studied Communication Systems Engineering at Institute of Space Technology (IST), Pakistan. He worked as Research fellow at IST from 2009 to 2013. With over 16 journal and national/international conference publications have deep interest in Hardware implementation of communication protocols ,Helix antennas and EMC.