FPGA Realization of Edge Detection Using Sobel Operator

In the field of engineering where intensive calculation is required it may not be good option to employ bulky CPU for computation. Because it uses much more resources for computation and other purpose. In such cases a dedicated hardware can be made to fulfil the requirement. Such hardware can be made on FPGA using HDL. So as an example an application of image processing is proposed in this project. Also in the field of image processing the role of FPGA is to provide faster computation time. Moreover edge detection is a fundamental need in the field of image processing (e.g. Finger Print Recognition, Live Broadcasting Video, X-ray, and CT Scan etc). So an edge detection technique using Sobel Operator is proposed to implement on FPGA. The algorithm for this technique will be programmed using Verilog HDL and simulation will be performed on Modelsim Simulator. After successful simulation the algorithm will be synthesized on FPGA using Xilinx Design and Development Software and the design will be tested on Xillinx FPGA board.

Autorentext

Dr. Upesh Patel is currently an Associate Professor and head of the Department of Electronics and Communication Engineering at Charotar University of Science and Technology, Gujarat. His research areas are Antenna Design, RF and Microwave technology. He published many peer-reviewed articles in reputable international journals and conferences.