Frequency Synthesis Of All Digital Phase Locked Loop

All Digital Phase Locked Loops (ADPLLs) have become more attractive because they yield better testability, programmability, stability, and portability over different processes and the ADPLLs can reduce the system turn around time. Phase-locked loop mechanisms may be implemented as either analog or digital circuits. Both implementations use the same basic structure. The implemented ADPLL has two operation modes which are frequency acquisition mode and phase acquisition mode. In frequency acquisition mode, the ADPLL achieves a fast frequency locking via the proposed feed-forward compensation algorithm. In phase acquisition mode, the ADPLL achieves a finer phase locking.

Autorentext

S.Saravanakumar VLSI Design Engineer, Caliber Embedded Technologies India (P) Ltd. I graduated M.E. VLSI Design in the year 2012 at Sri Ramakrishna Engineering College,Anna university,India. My area of interest is Analog & Low Power VLSI. Now I have currently working in the field of Low power VLSI design.