Hardware IP cores for Mathematical Operations

Currently complex mathematical operations have become vital and inevitable in all areas. We never imagine an application that does not need mathematical operations. Nevertheless almost all mathematical operations are not synthesizable (only the addition, subtraction and multiplication are synthesizable) by current synthesis tools like (ISE, Quartus, etc.); therefore, they are not implementable on FPGA. To overcome this dilemma,This books proposes synthesizable VHDL codes for the following mathematical operations: Chapter 1: The division Chapter 2: The square root Chapter 3: Exponential Function Chapter 4: Logarithmic Function Chapter 5: Trigonometric functions Chapitre 6 : arcsine and arccosine Chapter 7: Hyperbolic functions Chapter 8: nth root

Autorentext

Bouraoui ouni is the author of four books. He is also the author or co-author of several articles published in famous journals :JSA, Microprocessors and Microsystems , Computers & Electrical Engineering , Advances in Engineering Software , IET electronic letters, Design Automation for Embedded Systems