High Performance Multi-Channel High-Speed I/O Circuits

This book describes design techniques that can be used to mitigate crosstalk in high-speed I/O circuits. It examines the problem of crosstalk and ISI mitigation encountered as data rates have continued beyond 10Gb/s.

Describes technology and design ideas for power-efficient crosstalk cancellation in multi-channel high-speed I/O circuits Includes critical background knowledge related to channel ISI equalization circuits Provides crosstalk cancellation circuit methods that can be adapted efficiently to currently used equalization circuits in high-speed I/O receivers; key crosstalk cancellation blocks can be merged easily with automatic gain control (AGC) circuits in current I/O systems

Inhalt
Introduction.- 2x6 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Scheme in 130 nm CMOS Process.- 4x12 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Receiver in 65 nm CMOS Process.- Adaptive XTCR, AGC, and Adaptive DFE Loop.- Research Summary & Contributions.- References.- Appendix A: Noise Analysis.- Appendix B: Issues of Applying Consecutive 2x2 XTCR on Multi-Lane I/Os ( 4).- Appendix C: Transmitter-Side Discrete-Time FIR XTC Filter versus Receiver-Side Analog-IIR XTC Filter.- Appendix D: Line Mismatch Sensitivity.- Appendix E: Input Matching for 4x4 XTCR Receiver Test Bench.- Appendix F: Bandwidth Improvement by Technology Scaling.