HIGH RESOLUTION AND LOW JITTER FULL CUSTOM ADPLL ARCHITECTURES

All digital PLLs are being considered as an effective replacement due to high immunity of digital circuits to PVT variations. However, ADPLLs suffer from the problem of low resolution and high jitter/ phase noise apart from fundamental problems of complex design procedures. It was found through literature surveys and experimental verifications that there are still some challenges related to resolution, jitter/phase noise that need to be addressed, in the existing ADPLLs. Similarly, it was also found that there is a shortcoming in the models used to describe ADPLLs. In this regard, an extensive classification of existing ADPLL architectures was made. Some of the architectures found in literature were critically examined by redesigning and simulation verification at various levels of design with a wide set of simulation/emulation tools. Comparative analysis was done and shortcomings in each architecture were critically identified. Methods to improve resolution and phase noise were proposed and verified using simulation.

Autorentext

Dr. Mohd.Ziauddin Jahangir, completed his PhD from Osmania University Hyd, Bachelor's in ECE & Master's in ES&VLSID from OU. He is PI at MeiTY. Chip to Startup project C2S, CBIT.Prof. Chandra Sekhar Paidimarry has been taken over charge as I/c Principal, University College of Engineering (A), PI at MeiTY. C2S at OUCE.