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High-Speed Clock Network Design
Details
High-Speed Clock Network Design is a collection of design concepts, techniques and research works from the author for clock distribution in microprocessors and high-performance chips. It is organized in 11 chapters.
Klappentext
High-Speed Clock Network Design is a collection of design concepts, techniques and research works from the author for clock distribution in microprocessors and high-performance chips. It is organized in 11 chapters.
Zusammenfassung
High-Speed Clock Network Design is a collection of design concepts, techniques and research works from the author for clock distribution in microprocessors and high-performance chips. It is organized in 11 chapters.
Inhalt
1 Introduction.- 2 Overview to Timing Constraints.- 3 Sequential Clocked Elements.- 4 Design Methodology for Domino Circuits.- 5 Clock Generation and De-Skewing.- 6 Microprocessor Clock Distribution Examples.- 7 Clock Network Simulation Methods.- 8 Low-Voltage Swing Clock Distribution.- 9 Routing Clock on Package.- 10 Balanced Clock Routing Algorithms.- 11 Clock Tree Design Flow in Asic.- Reference.
Weitere Informationen
- Allgemeine Informationen
- GTIN 09781441953360
- Genre Elektrotechnik
- Auflage Softcover reprint of hardcover 1st edition 2003
- Sprache Englisch
- Lesemotiv Verstehen
- Anzahl Seiten 196
- Größe H235mm x B155mm x T11mm
- Jahr 2010
- EAN 9781441953360
- Format Kartonierter Einband
- ISBN 1441953361
- Veröffentlichung 02.12.2010
- Titel High-Speed Clock Network Design
- Autor Qing K. Zhu
- Gewicht 306g
- Herausgeber Springer US