High Speed Low Offset Power Efficient Dynamic CMOS Comparator

This book describes various Trade-Offs in Comparator Design especially in Analog & Mixed Signal VLSI Design. The various comparator designs have been illustrated in details with detailed analysis. Further, the analysis and design of a high speed low offset power efficient dynamic CMOS Comparator based on Fully Differential and Double Tail structure is presented. A novel concept of Fully Differential Double Tail Dynamic comparator (FDDTDC) realized with high-speed, low offset with optimized power and area than that of the conventional dynamic comparators is proposed. The end result reveals the potential of new proposed comparator architecture and design methodology for high-speed low offset power efficient applications.

Autorentext

Dr. Priyesh P. Gandhi completed Ph. D. in VLSI Design from Nirma University, Ahmedabad, Gujarat, India in year 2018. He is currently working as a Principal, Sigma Institute of Engineering, Vadodara, India since March 2019. He has published more than 45 research papers in reputed international journals and conferences.