Impact of geometry on charge trap non volatile memories

The present research work is dedicated to quantify the impact of the geometry on memory performances in charge trap Flash memory devices. The main axes of research have been first to use a large set of electrical measurements, modeling and simulation made on planar devices. Then the acquainted knowledge has been applied to more complicated geometries and in particular Charge Trap Gate-All-Around devices (CT GAA), Charge Trap FinFET (CT FinFET) devices and CT Split-Gate devices. The two first are investigated for standalone application whereas the third one is investigated for embedded applications.

Autorentext

Etienne Nowak achieved is PhD at CEA-Leti, France. From 2010 to 2014, as senior engineer at Samsung Semiconductors, Korea, he simulated the first fourth Vertical NAND generations. Since 2014, he is a project manager at CEA-Leti, pursuing the integration of next-generation memory devices. He published over 20 peer-review papers and owns 2 patents.