Impact of Leakage Power Reduction Techniques on Parametric Yield

With the advancement of process technology for fabrication of integrated circuits, the magnitude of variations in process parameters have increased and the parametric yield loss problem has become a serious concern of the fabrication houses. Thus, the traditional techniques for power and delay optimization in design automation tools can no longer be used effectively. This has opened up a challenge to the chip designers to design integrated circuits, which are variation tolerant and thereby having higher parametric yield. In this monograph, a single threshold voltage based approach is proposed that exhibits runtime leakage power reduction comparable to the existing dual threshold voltage assignment approaches and at the same time the proposed approach is less sensitive to process parameter variations. Again, this logic-level runtime leakage reduction technique is combined with multiple supply voltage assignment during high-level synthesis for total power reduction. It is believed that the proposed leakage power reduction technique will be useful in digital circuit design flow (logic-level and high-level syntheses) under process parameter variation.

Autorentext

Sudip Roy received BSc in Physics in 2001 and BTech in Computer Science and Engineering in 2004 from University of Calcutta, India. In 2009, he received MS and currently he is pursuing PhD from IIT Kharagpur, India. His research interests include computer-aided-design and testing of digital VLSI chips and digital microfluidic biochips.