Impact of Spacer Engineering on Performance of Junctionless Transistor

The scaling of traditional planar CMOS devices is becoming difficult due to increasing gate leakage and subthreshold leakage. Multigate FETs have been proposed to overcome the limitations associated with the scaling of traditional CMOS devices below 100nm region. The multiple electrically coupled gates and the thin silicon body suppress the short-channel effects, thereby lowering the subthreshold leakage current in a multi-gate MOSFET. However, fabrication complexity increases for inversion mode (IM) FinFET devices due to ultra-steep doping profiles requirement. Junctionless transistor (JLT) overcomes the limitations associated with the creation of ultra-steep doping profiles during fabrication and short channel effects. In order to further reduce the SCEs, spacers at the both sides of gate are used that minimizes the leakage current. In this proposed work, JLT is designed with the use of spacer engineering i.e. changing the Lext, spacer's proportion as well as the dielectric values ( ) of spacer material and its performance are evaluated from device characteristics using TCAD software tool.

Autorentext

Prabhjot Kaur arbeitet an der Universität von Uttaranchal. Sie hat großes Interesse an der Datenanalyse mit ML.Dr. Amit Awasthi arbeitet an der University of Petroleum & Energy Studies und verfügt über mehr als 15 Jahre Berufserfahrung. Er hat 40 Forschungsarbeiten in SCI-Zeitschriften mit einem Impact-Faktor von 75, einem i10-Index von 18 und Zitierungen von 1000 veröffentlicht.