Investigation of Optimum Design at Nanoscale Reconfigurable Devices

The purpose of designing SiNWFET using dual k spacer is to reduce the SCE and to increase the on-off current ratio. The proposed device effectively combines different mechanisms of lowering the sub threshold swing (SS). By using spacers and schottky junction we get more efficient system to improve the design metrics like electric density, potential and resistance of the device. Our simulation results show that though high- spacer improves device performance like ION, S/S,So that performance of the device improved and reduces the losses.In the existed SiNWFET as Scaling down the thickness of gate oxide is not found to be a good idea, as it causes a reduction in ON-OFF current ratio though S/S remains mostly unaffected. In normal FET without spacer it has high off current and increased short channel effect. In the existed the off current is more and performance is also reduced. Review, synthesis and conduct of the literature are actual metrics of a standard or post graduate attempt of literature review. A well organized and formulated review will give best light on contribution and framing of the good methodology.

Autorentext

N.S.Murti Sarma is a professor of Electronics and communications Engineering of Hosting College. P.Pradeep is identifed as a successful graduate research scholar by research assessment committee . Dr.S.P.Venumadhavarao is director of R&D of SNIST, Hyderabad.