Investigations On Performance Evaluation Of CMOS VLSI

The progression in very large scale integration, billions of transistors and components can be placed on a single semiconductor chip for implementation of complex circuitry. The growth in recent technology is towards miniaturization of semiconductor devices, which have several noticeable hindrances in heat dissipation, power utility, chip area and efficiency of the devices. As the technology advances more into deep submicron level, feature sizes, power dissipation due to leakage current are increasing at an alarming rate. Numerous projections show that leakage power will develop into analogous to dynamic power dissipation in coming years; however dynamic power is also increasing and still dominates. The optimal solution for solving these hindrances is to analyze the performance of VLSI circuit designed using different CMOS technologies.

Autorentext

Dr.T.SHEELA obtained her Doctorate degree in VLSI Design in 2015 from Vinayaka Missions Research Foundation, Salem and Master degree from Anna University in 2008. She is an Associate Professor/ECE at VMKVEC, Salem. She has published several Journals and Book. Her research interests include VLSI circuits, Digital circuit and Electronic circuits.