Iterative Decoding in Analog VLSI

This book explores theoretical and practical aspects
of iterative decoding algorithms when they are
implemented on analog continuous-time platforms.
Analog continuous-time iterative decoding was
proposed a few years ago to improve the
power/speed ratio of decoder chips that decode
capacity achieving codes. It was commonly
believed that replacing discrete-time processing
modules with analog circuits would not change the
dynamics of the iterative decoder. On the contrary,
it is shown that not only does continuous-time
iterative decoding have different dynamics, but also
its error correcting performance can surpass that of
conventional iterative decoders.
Furthermore, novel processing modules for
implementing affordable
high-speed strongly inverted CMOS analog min-sum
iterative decoders are presented. This is favorable
because previously reported analog decoders were
either BiCMOS or weakly inverted CMOS designs. The
former could be fast but is rather expensive and
the latter would be low-power but it is not fast
enough for many applications.

Autorentext

is a Sr. researcher at McGill University, Montreal, Canada and works on design and implementation of iterative decoders.He received the B.Sc. and M.Sc. degrees in Electrical Engineering from Isfahan University of Technology, Isfahan, Iran and the Ph.D. degree from Carleton University, Ottawa, Canada. Dr. Hemati is senior member of IEEE.

Klappentext

This book explores theoretical and practical aspectsof iterative decoding algorithms when they areimplemented on analog continuous-time platforms.Analog continuous-time iterative decoding wasproposed a few years ago to improve thepower/speed ratio of decoder chips that decodecapacity achieving codes. It was commonlybelieved that replacing discrete-time processingmodules with analog circuits would not change thedynamics of the iterative decoder. On the contrary,it is shown that not only does continuous-timeiterative decoding have different dynamics, but alsoits error correcting performance can surpass that ofconventional iterative decoders. Furthermore, novel processing modules forimplementing affordablehigh-speed strongly inverted CMOS analog min-sumiterative decoders are presented. This is favorablebecause previously reported analog decoders wereeither BiCMOS or weakly inverted CMOS designs. Theformer could be fast but is rather expensive andthe latter would be low-power but it is not fastenough for many applications.