Leakage currents in MOS transistor

In order to bring the classification of leakage minimization approaches, analyzed based on their fundamental design and mechanism, such as biasing technique, power gating, and multi-threshold techniques. A brief summary of different leakage control schemes with their merits and demerits along with the limitations by using these schemes are presented. In this survey, origins of leakage currents in a short-channel device and various leakage control techniques for ultra-low power SRAM design are discussed. The rest of the book chapter is organized as follows. In section 2 presents the origin of leakage current in a short-channel device. Various biasing techniques for leakage control SRAM are discussed in section 3. Emerging power gating techniques for low power SRAM designs are presented in section 4. Asymmetrical SRAM designs with multi-threshold transistor are described and comparisons of various low power techniques are tabulated in section 5. Finally, the survey chapter concludes in section 6.

Autorentext

P. K. Bikki (MIETE, MIEEE) received M. Tech Degree in VLSI design from M. A. National Institute of Technology, Bhopal in 2012. He is currently pursuing Ph.D. Degree in Motilal Nehru National Institute of Technology, Allahabad. His current research interests are in the area of Low power VLSI Design, and design issues in high-performance.