Logic Optimization and Synthesis Techniques with Area-Power Trade-offs

In recent times, power consumption has been recognized as an important issue in implementing battery-operated portable devices. Power consumption is being addressed in all levels of VLSI design. The saving will be higher if power issues are taken care of early in the design cycle. This has motivated us to consider power issue at the logic level. Due to the exponential nature of leakage in the subthreshold regime operation of transistors, leakage current can no longer be ignored. In this work we have adressed both the dynamic and leakage power consumption of the circuit. The problems addressed in this work handle multiple objectives, such as area, power etc. and a combination of these. Thus, based on relative priority of one over the other, the circuits can be optimized. We have developed both combinational and sequential logic synthesis techniques targeting the trade-offs in the final circuit. Two, and multilevel combinational circuit synthesis and optimization using GA have been presented. Effectiveness of power-gating technique to reduce power dissipation has been examined. A technology specific approach to reduce standby leakage has been developed.

Autorentext

Sambhu Nath Pradhan has obtained Ph.D degree from the Dept. of E and ECE, IIT Kharagpur in 2010. Currently he is working as an Assistant Professor in the Dept. of Electronics and Communication Engineering, NIT Agartala. His area of research includes low-power VLSI design and testing.