Logic Synthesis for Finite State Machines Based on Linear Chains of States

This book discusses Moore finite state machines (FSMs) implemented with field programmable gate arrays (FPGAs) including look-up table (LUT) elements and embedded memory blocks (EMBs). To minimize the number of LUTs in FSM logic circuits, the authors propose replacing a state register with a state counter. They also put forward an approach allowing linear chains of states to be created, which simplifies the system of input memory functions and, therefore, decreases the number of LUTs in the resulting FSM circuit. The authors combine this approach with using EMBs to implement the system of output functions (microoperations). This allows a significant decrease in the number of LUTs, as well as eliminating a lot of interconnections in the FSM logic circuit. As a rule, it also reduces the area occupied by the circuit and diminishes the resulting power dissipation.

This book is an interesting and valuable resource for students and postgraduates in the area of computer science, as well as for designers of digital systems that included complex control units

Presents original synthesis and optimization methods taking into account the peculiarities of a control algorithm and finite state machine (FSM) model in use Discusses the hardware implementation of control algorithms represented by graph schemes of algorithm Takes into account the peculiarities of an FSM model used for the interpretation of a control algorithm, as well as the features of hardware in use Provides numerous examples showing the design of FSMs using the proposed methods Includes examples illustrated by logic circuits Includes supplementary material: sn.pub/extras

Inhalt

Introduction.- Finite state machines and eld-programmable gate arrays.- Linear chains in FSMs.- Hardware reduction for Moore UFSMs.- Hardware reduction for Mealy UFSMs.- Hardware reduction for Moore NFSMs.- Hardware reduction for Moore XFSMs.