Low Leakage Variability Aware Techniques for CMOS Logic Circuits

The broad necessity of battery operated portable applications need to explore the low power VLSI research field. The portable applications such as calculator, hearing aids, portable military equipments, laptop, notebook, mobile phone, implantable pacemaker, wristwatches, etc. have the huge market in current scenario. The longer battery performs the better for all such applications. Minimization of the overall power dissipation gets the battery performance. Leakage power dissipation which is the component of total power dissipation is the dominant part in ultra-DSM regime. Therefore, this book has proposed several circuit level leakage reduction techniques for CMOS circuits. Process variability is considerably increasing with technology scaling and causes performance fluctuations. Parameter variations are affecting the leakage current in several ways in ultra-DSM regime. The effect of PVT variations is considered to measure the reliability issues. All proposed approaches are based on individual CMOS logic. These CMOS logics can be employed to design any low leakage logic circuit.

Autorentext

Vijay Kumar Sharma (B. Tech., M.Tech. PhD) is doing research in the areas of low power high performance CMOS circuits and variations-aware integrated circuit design. His research interest include device circuitco-design and circuit system co-design. He has contributed no. of research articles in reputed journals/conferences in his research area.