Low Power and High Performance Array Multiplier

Arithmetic circuits, like adders and multipliers, are one of the basic components in the design of communication circuits. In fact 8.72% of all instructions in a typical scientific program are multiplies. The multiplier is a fairly large block of a computing system. Multiplier is not only a high-delay block but also a significant source of power dissipation. That s why, if one also aims to minimize power consumption, it is of great interest to identify the techniques to be applied to reduce delay by using various delay optimizations. Array architecture is a popular technique to implement the multipliers due to its compact structure. In this book, six array multiplier circuits using different AND cells and XOR gates have been designed, simulated, analyzed and compared. This analysis should help shed some light on the low power and high throughput 2×2 array multiplier cells and should be especially useful for post graduate students and research scholars working in low power VLSI circuit design field.

Autorentext

Tripti Sharma, M.Tech., Ph.D. (pursuing): Achieved M.Tech.(VLSI Design) degree from MITS (Deemed University), Pursuing Ph.D. from Gyan Vihar University, Jaipur, Currently working as an Assistant Professor at MITS (Deemed University), Lakshmangarh, INDIA.