Low Power Asynchronous Viterbi Decoder

This book is about the designing of low power asynchronous Viterbi Decoder. Due to requirements of high speed, low power, low weight and long battery life a low power Viterbi decoders has a great demand in the communication field.In mobile communication system, the Viterbi decoder occupies greater chip area which directly related to the power loss. So we designed such a system which consumes less dynamic power and can be used in low power applications. Instead of using Global Clock the system is designed using Local clock by employing low power technique as 2 phase Level Encoded Dual Rail encoding with Minimum Transition Hybrid Register Exchange decoding method to reduce the switching activity and to avoid unnecessary memory operations so as to reduce dynamic power of decoder. The designed system has been tested with different input vectors and dynamic power is calculated for Synchronous and Asynchronous Viterbi decoder. The Comparative Power Analysis by different decoding methods proved that Asynchronous Viterbi decoder has less power consumption than Synchronous Viterbi Decoder.

Autorentext

La Dra. Surekha Tadse trabaja como profesora adjunta en el G H Raisoni College of Engineering, Nagpur, (MH), India. Su área de interés es la comunicación y VLSI. Ha publicado más de 30 artículos en revistas y conferencias de renombre.El Dr. Sanjay Haridas trabaja como profesor y decano académico en el J D College of Engineering and Management, Nagpur.