Low Power Cmos Based Flash ADC

In the present work, a 4-bit and a 6-bit 100 MS/s flash analog to digital converter for low power SoC application is presented. CMOS inverter has been used as a comparator for low power design. By adjusting the ratio of channel width and length, the switching threshold of the CMOS inverter is varied to detect the input analog signal. The proposed architecture has a unique feature like power supply rejection ratio (PSSR) which plays very critical role in traditional analog design. PSRR is introduced in the digital counterpart in the present design.

Autorentext

Sudakar SIngh Chauhan has received his M.Tech degree in VLSI Design Automation and Technique at NIT Hamirpur in 2009. Since then he has worked in CEERI Pilani in different projects in the field of Analog Design. He is working as an assistant professor at Graphic Era University. He is the author of several articles published in reputed journals.