Low Power Fault Tolerant Latches and Flip-flops

Today, the latches and flip-flops are widely used for data storage. This book focus on review, study and design of fault tolerant circuits to reduce circuit level faults and protect a circuit from faults. In this book, eight novel low power fault tolerant latches and four glitch free flip-flops are discussed. The latch configurations are designed with the 1P-2N structure and 2P-1N structure or 1P-2N structure, 2P-1N structure and C-element structure. If any transient fault affects one of the structure, then it is corrected by the other structure. The glitch free dual edge triggered flip flops are the novel and unique designs. Till now, existing DET-FF designs are constructed by using either C-element circuit or 1P-2N structure or 2P-1N structure but proposed novel designs are designed by using the combination of C-element circuit and 2P-1N structure or C-element circuit and 1P-2N structure. The glitch free novel DET-FFs provide the totally glitch free output and can increase the system efficiency. The potential novelty of this work is that the presented novel designs can reduce the 50% power consumption and contribute to the total system power savings.

Autorentext

Dr. Sumitra Singar hat 2018 an der Mody University of Science and Technology, Lakshmangarh, Sikar, Rajasthan, Indien, promoviert. Sie hat ihren M.Tech. in VLSI Design im Jahr 2013 abgeschlossen. Sie hat 2010 ihren B.Tech. an der Technischen Universität von Rajasthan, Rajasthan, Indien, gemacht.