Low Power Interface Circuits between Adiabatic and Standard CMOS Logic

The clocking schemes and signal waveforms of Adiabatic Circuits are different from those of Standard CMOS circuits. The Adiabatic Logic and Standard CMOS circuits do exist on a single chip to utilize the strength of both approaches. The interface circuits that convert signals between Adiabatic Logic and Standard CMOS circuits are inherent requirement. The text investigates design approaches of Adiabatic- CMOS and CMOS- Adiabatic interface circuits. Several new low power Adiabatic-CMOS and CMOS-Adiabatic interfaces are introduced in this text. Tanner EDA tool on BSIM3V3 90nm and 130nm CMOS technologies has been used to calculate the power consumption and power delay product of various circuits over temperature, frequencies and power supply voltages. The comparison of proposed approaches has been done with the all other approaches available in the literature on various circuit parameters. The write up concludes the efficient design approaches for interface circuits in terms of power consumption and power delay product.

Autorentext

Neha Arora received the B.E. degree in ECE from Rajasthan University, India, in 2007, and completed the academics of M.Tech in VLSI Design from FET, MITS in 2010. She is working as Assistant Professor in the Department of ECE, from 2007 to till date at Mody Institute of Technology & Science, Lakshmangarh (Deemed University), Rajasthan (INDIA).