Managing Dynamic Non-Uniform Cache Architectures

Researchers from both academia and industry agree that future CMPs will accommodate large shared on-chip last-level caches. However, the exponential increase in multicore processor cache sizes accompanied by growing on-chip wire delays make it difficult to implement traditional caches with a single, uniform access latency. Non-Uniform Cache Access (NUCA) designs have been proposed to address this situation. A NUCA cache divides the whole cache memory into smaller banks that are distributed along the chip and can be accessed independently. Response time in NUCA caches does not only depend on the latency of the actual bank, but also on the time required to reach the bank that has the requested data and to send it to the core. So, the NUCA cache allows those banks that are located next to the cores to have lower access latencies than the banks that are further away, thus mitigating the effects of the cache s internal wires.

Autorentext

Javier Lira started his PhD in January 2008. He did research on memory management for multi-core architectures, focusing on Non-Uniform Cache Architectures (NUCA), under the supervision of Prof. Carlos Molina (URV) and Prof. Antonio González (Intel and UPC). He graduated in November 2011, and is currently working at Intel Barcelona Research Center.