Mathematical Layout of a Graph Embedding

An important feature of an interconnection network is its ability to efficiently simulate programs written for other architectures. Such a simulation problem can be mathematically formulated as graph embedding. Graph embedding is an important technique for studying the computational capabilities of processor interconnection networks and task distributions, which is a recent focus of research in the parallel processing area. The quality of an embedding can be measured by certain cost criteria, namely dilation and wire-length (layout). Dilation is the measure for the communication time needed when simulating one network on another. The layout of a graph embedding arises from the VLSI designs, biological models that deal with cloning and visual stimuli, parallel architecture and structural engineering. In this book we give the techniques to compute the layout of a graph embedding and apply this for certain well known interconnection networks such as circulant networks, hypercubes, folded hypercubes, grid networks and generalized Petersen graphs.

Autorentext

Dr.Micheal Arockiaraj is an Assistant Professor of Mathematics in Loyola College, Chennai. His research interests include study of embedding parameters in interconnection networks and topological indices of chemical graphs. Dr.Indra Rajasingh who is currently a Professor of Mathematics in VIT University, Chennai, India, was his research supervisor.