Modeling, Verification and Exploration of Task-Level Concurrency in Real-Time Embedded Systems

system is a complex object containing a significant percentage of elec A tronics that interacts with the Real World (physical environments, humans, etc. ) through sensing and actuating devices. A system is heterogeneous, i. e. , is characterized by the co-existence of a large number of components of disparate type and function (for example, programmable components such as micro processors and Digital Signal Processors (DSPs), analog components such as AID and D/A converters, sensors, transmitters and receivers). Any approach to system design today must include software concerns to be viable. In fact, it is now common knowledge that more than 70% of the development cost for complex systems such as automotive electronics and communication systems are due to software development. In addition, this percentage is increasing constantly. It has been my take for years that the so-called hardware-software co-design problem is formulated at a too low level to yield significant results in shorten ing design time to the point needed for next generation electronic devices and systems. The level of abstraction has to be raised to the Architecture-Function co-design problem, where Function refers to the operations that the system is supposed to carry out and Architecture is the set of supporting components for that functionality. The supporting components as we said above are heteroge neous and contain almost always programmable components.

Klappentext

The combination of VLSI process technology and real-time digital signal processing (DSP) has brought a break-through in information technology. This rapid technical (r)evolution allows the integration of ever more complex systems on a single chip. However, these technology and integration advances have not been matched by an increase in design productivity, causing technology to leapfrog the design of integrated circuits (ICs). The success of these emerging systems-on-a-chip' (SOC) can only be guaranteed by a systematic and formal design methodology, possibly automated in computer-aided design (CAD) tools, and effective re-use of existing intellectual property (IP). In this book, a contribution is made to the modeling, timing verification and analysis, and the automatic synthesis of integrated real-time DSP systems. Existing literature in these three domains is extensively reviewed, making this book the first to give a comprehensive overview of existing techniques. The emphasis throughout the book is on the support and guaranteeing of the real-time aspect and constraints of these systems, which avoids time consuming design iterations and safeguards the ever shrinking time-to-market. The proposed Multi-Thread Graph' (MTG) system model features two-layers, unifying a (timed) Petri net and a control-data flow graph. Its unique interface between both models offers the best of two worlds and introduces an extra abstraction level hiding the operation-level details which are unnecessary during global system exploration. The formulated timing analysis and verification approach supports the calculation of temporal separation between different MTG entities as well as realistic performance metrics for highly concurrent systems. The synthesis methodology focuses on managing the task-level concurrency (i.e. task scheduling), as part of a proposed overall system design meta flow. It emphasizes performance and timing aspects (`timeliness'), while minimizing processor cost overhead as driven by high-level cost estimators. The approach is new in the abstraction level it employs, and in its optimal hybrid dynamic/static scheduling policy which, driven by cost estimators, selects the scheduling policy for each behavior. At the low-level, RTOS synthesis generates an application-specific scheduler for the software component. The proposed synthesis methodology (at the task-level) is asserted to yield most optimal results when employed before the hardware/software partition is made. At this level, the distinction between these two is minimal, such that all steps in the design trajectory can be shared, thereby reducing the system cost significantly and allowing tighter satisfaction of timing/performance constraints. From the Foreword: This book is the first comprehensive treatment of software, and more general, system, generation (synthesis) techniques based on formal models. It can be used as a very valuable reference to understand the development of the field of embedded software design, and of system design and synthesis in general. The book offers an invaluable help to researchers and practitioners of the field of embedded system design. Prof. Alberto Sangiovanni-Vincentelli, Edgar L. and Harold H. Buttner Professor of Electrical Engineering and Computer Science , University of California, Berkeley, Chief Technology Advisor, Cadence Design Systems.

Inhalt

1. Introduction.- 1. Systems-on-a-chip.- 2. Heterogeneous real-time embedded systems.- 3. Unified meta design flow for multi-media and telecom applications.- 4. Design methodology & CAD design support.- 5. Overview of the book.- 2. Related Work and Contemporary Approaches.- 1. Manual approach.- 2. Real-time operating systems.- 3. Processor architecture integration.- 4. Task concurrency management.- 5. Motivation for a new approach.- 3. System Representation Model.- 1. Model requirements.- 2. Related Work Models considering time.- 3. Basic Multi-Thread Graph model.- 4. MTG model extended with data communication.- 5. MTG model extended with timing.- 6. MTG model extended with hierarchy.- 7. Miscellaneous extensions.- 8. Advantages of the MTG model.- 9. Future extensions.- 10. Summary.- 4. Timing Analysis.- 1. Problem formulation.- 2. Related work Timing verification.- 3. Related work Timing analysis.- 4. Related work Performance analysis.- 5. MTG classification.- 6. MTG separation analysis.- 7. MTG latency and response time analysis.- 8. MTG rate analysis.- 9. MTG boundedness analysis.- 10. Summary.- 5. System Synthesis Methodology.- 1. Methodology overview.- 2. MTG model extraction.- 3. Resource estimation.- 4. Task concurrency management Thread frame clustering.- 5. Task concurrency management Thread frame scheduling.- 6. Task concurrency management Execution model selection.- 7. RTOS synthesis.- 8. Summary.- 6. Conclusions.- 1. Motivation.- 2. Contributions.- 3. Future work.- Appendices.- Definitions.- 1. Multi-sets.- 2. MTG definitions and properties.- 2.1 Definitions.- 2.2 Behavioral and structural properties.- 3. Algebras.- 3.1 Number algebras.- 4. Relations and partial orders.- 4.1 Binary relations.- 4.2 Partial orders.- 5. Automata.