Modulated Frequency Synthesizers

This book presents a wideband GFSK-modulated
fractional-N frequency synthesizer which using the
two-point delta-sigma modulation (TPDSM). Two
bottlenecks in this design have been rigorously
investigated. One is the nonlinear performance of
fractional-N frequency synthesizers. The other one
is the inherent gain and delay mismatch between the
two modulation points. Both nonlinear and mismatch
factors dominate the modulation accuracy in the
closed phase-locked loop (PLL). The proposed
formulation can successfully predict the
dependencies of the modulation accuracy on both
factors. The comparison of the averaged frequency
deviation and frequency-shift-keying (FSK) error
between theory and measurement shows excellent
agreement. The modulated frequency synthesizer
implemented in this study can achieve a 2.5 Mbps
data rate as well as a 15 s PLL stable time with
only 2.2 % FSK error under good design and operating
conditions.

Autorentext
Kang-Chun Peng, PhD: Studied Electrical Engineering at National Sun Yat-sen University. Assistant Professor of Computer and Communication Engineering at National Kaohsiung First University of Science and Technology, Taiwan.

Klappentext
This book presents a wideband GFSK-modulated fractional-N frequency synthesizer which using the two-point delta-sigma modulation (TPDSM). Two bottlenecks in this design have been rigorously investigated. One is the nonlinear performance of fractional-N frequency synthesizers. The other one is the inherent gain and delay mismatch between the two modulation points. Both nonlinear and mismatch factors dominate the modulation accuracy in the closed phase-locked loop (PLL). The proposed formulation can successfully predict the dependencies of the modulation accuracy on both factors. The comparison of the averaged frequency deviation and frequency-shift-keying (FSK) error between theory and measurement shows excellent agreement. The modulated frequency synthesizer implemented in this study can achieve a 2.5 Mbps data rate as well as a 15 µs PLL stable time with only 2.2 % FSK error under good design and operating conditions.