MOS Based Adder Design for Multiplication Algorithms

"One among the current trends in VLSI design is to minimize implementation area either by decreasing the feature size or by decreasing the number of devices used to achieve the desired operation. However while doing so it is expected that the voltage value of the designated outputs gets degraded, due to which they might not be suitable for cascaded circuit design. Thus this work provided some basic design strategies that help us achieve circuit minimization of an adder circuit keeping in view its capability of driving the following cascaded stages in applications such as multiplier circuits."

Autorentext

Afshan Amin Khan Received B.Eng. Degree in ECE from Islamic University of Science and Technology, Awantipora, J&K in year, 2011 and M .Tech Degree in ECE from Lovely Professional University, Jalandar, Punjab in year, 2014. He is currently a Research Scholar in the Department of CSE at National Institute of Technology,Srinagar,J&K.