Multiplexer (MUX) Free Carry Select Adder

The book presents Multiplexer (MUX) free Carry Select Adder (CSA) using First Zero Finding (FZF) logic circuit. We have further modified the system such that second stage RCA block and final stage MUX are eliminated by FZF logic circuit due to which performance and respective parameters are expected to improve. Based on the analysis and observation of the result obtained major improvement is seen in power and area. MUX free CSA design saves an average 41.45%, 48.26%, 52.21%, 33.82% % of area, leakage power, power and PDP respectively however 38.59% delay gets increases compared to conventional design of CSA. All the circuits are implemented in Cadence virtuoso using 180nm CMOS process technology.

Autorentext

Shivendra Pandey travaille comme consultant SAP chez AtoS Global IT Solution, en Inde, et a également travaillé pour un client à Singapour. Il a obtenu un M.Tech en technologie VLSI de l'Université professionnelle de Lovely, Punjab, Inde et un B.Tech en ingénierie électronique et de communication du Collège d'ingénierie de Rewa, Rewa, Inde.