Network on chip based hardware accelerators for Computational Biology

The focus of this work is the design and performance evaluation of Network on Chip (NoC) based multi-core hardware accelerators for computational biology. Sequence analysis and phylogenetic reconstruction are the two problems in this domain which have been addressed here. An effective approach to speed up such operations is to integrate a very high number of processing elements in a single chip so that the massive scales of fine-grain parallelism inherent in this application can be exploited efficiently. Network-on-Chip (NoC) is a very efficient method to achieve such large scale integration. Specifically, we (i) propose optimized NoC architectures for different sequence alignment algorithms that were originally designed for distributed memory parallel computers, (ii) a custom NoC architecture for solving the breakpoint phylogeny problem (iii) provide a thorough comparative evaluation of their respective performance and energy dissipation.

Autorentext

Souradip Sarkar is currently with the Measurement Research Labs within Agilent Technologies. Prior to this he was with the Exascience labs (Intel labs, Europe). He completed his PhD from Washington State University in 2010. His primary interests are in reconfigurable parallel architectures and algorithms, Signal Processing, and System-on-Chips.