New Approach to Low Power Full Adder Cell

In recent years, low power design has become one of the prime focuses for digital VLSI circuits. As technology scales down, leakage currents in contemporary CMOS logic have become one of the main power consumers. Contrary to conventional methods for power reduction, operation of digital circuits in the subthreshold region minimizes power consumption in low-frequency systems. This book is based on pre-layout and post-layout simulations of a modified 9T full adder and 9T full adder circuit in subthreshold as well as super threshold region. The 9T circuit consists of a new logic, which is used to implement Sum module. This design remarkably reduces power consumption hence improves power-delay product (PDP) and temperature sustainability along with noise immunity and threshold loss when compared with the modified 8T adder. This book, therefore, provides a new metric of implementing high performance full adder circuit. This analysis should help shed some light on the new and exciting approach for achieving low power and high throughput adder cell and should be especially useful to post graduate students and research scholars in VLSI circuit design field.

Autorentext
Tripti Sharma, M.Tech., Ph.D. (pursuing):Achieved M.Tech.(VLSI Design) degree from MITS (Deemed University),Pursuing Ph.D. from Suresh Gyan Vihar University,Jaipur, Currently working as an Assistant Professor at MITS, Lakshmangarh, INDIA, Has more than 42 papers published in International Journals/International and National Conferences.