Next-Generation Floating-Point Arithmetic Unit

The Next-Generation Floating-Point Arithmetic Unit Using QCA for Low-Power Applications explores the use of Quantum-dot Cellular Automata for implementing a Floating-Point Arithmetic Unit at the Nano-scale, overcoming limitations of CMOS technology. The research involves designing efficient QCA-based 1-bit and 8-bit full adders, multipliers, and a novel Tree-Based Stack-Type comparator. The proposed FPAU is tested through the implementation of a Fast Fourier Transform algorithm, demonstrating significant improvements in area, power dissipation, and delay compared to existing CMOS-based architectures.

Autorentext

Dr. A Arunkumar Gudivada: currently working as Associate Professor in the Department of ECE of ACET (A), Surampalem, India. Dr. E. Jagadeeswara Rao: currently he works as an Assistant Professor in the Department of ECE at GVPCE (A), Visakhapatnam, and Andhra Pradesh, India.