Optimisation of Grooved Gate MOSFETS for SUB-100 NM VLSI Technology

The short-channel and hot-carrier effects that arise when MOSFET devices are scaled down to very short channel lengths is a major topic of research in the area of VLSI technology. Grooved gate MOSFETS alleviate many of these. Here a systematic study of the major electrical characteristics of grooved gate device is done at gate lengths of 100 nm. An optimised process flow is presented to overcome two of its major drawbacks - higher gate-to-source/drain parasitic capacitance and lack of a self-aligned and integrated gate structure. The resulting device exhibits significantly enhanced characteristics. An analytical model for the gate-to-source/drain capacitance characteristics of the grooved gate device is then presented. It features an extrinsic capacitance model that incorporates the strong bias dependence of overlap capacitance and deals with the issues involved in optimisation and analysis of not only such novel device structures but source/drain engineered conventional planar devices also. This work should be especially useful to professionals and students in Microelectronics field who are engaged in processing, characterization and modelling of deep sub-micron VLSI devices.

Autorentext

Dr. Sreelal Sreedharan Pillai: M.Tech and Ph.D. from Indian Institute of Technology, Chennai in 1992 and National University of Singapore in 2004. R&D Engineer, Avionics in Indian Space Research Organization. Dr. Samudra Ganesh Shankar: Assoc. Professor with National University of Singapore. M.S. and Ph.D. from Purdue University in 1982 and 1985.