Parallel Prefix Adder Architecture

Two-operand binary addition is the most widely used arithmetic operation in modern data path designs. To improve the efficiency of this operation, it is desirable to use an adder with good performance and area trade-off characteristics. This work presents an efficient carry- look-ahead adder architecture based on the parallel-prefix computation graph. In this book, we define the notion of triple-carry-operator, which computes the generateand propagate signals for a merged block which combines three adjacent blocks. We use conjunction with the classic approach of the carry-operator to compute the generate and propagate signals for a merged block combining two adjacent blocks. The timing-driven nature of the proposed design reduces the depth of the adder. In addition, we use a ripple-carry type of structure in the non-timing critical portion of the parallel-prefix computationnetwork.

Autorentext

Dr M. Mahaboob Basha and Dr Sibghatullah Khan hold Ph.D in Electronics and Communication Engineering. They are working as Associate Professor in Department of Electronic and Communication Engineering, Sreenidhi Institute of Science and Technology, Hyderabad India.