Partial Reconfiguration with AES Algorithms

Field Programmable Gate Array (FPGA) market is growing rapidly with various applications in different industries. This work reports Partial Reconfiguration (PR) by which FPGA can dynamically reconfigure. PR could be useful to reduce area requirements and upsurge systems versatility. Today cryptographic algorithms need to modify for security reason. Furthermore dedicated hardware required to implement cryptographic application is costly. Hence, the solution is proposed with the help of reconfigurable computing. Herein partial reconfiguration is explored with AES (Advanced Encryption Standard) algorithm, to achieve the goal of secureness in cryptography & for this we have developed new methodology of key encryption/decryption and achieved very good performance.

Autorentext

Rashmi Mahajan ha realizado un doctorado y un máster en tecnología VLSI en la Universidad Kavayitri Bahinabai Chaudhari North Maharashtra (KBCNMU), en Jalgaon, en ingeniería electrónica. Tiene más de 20 publicaciones en varias revistas nacionales e internacionales. Está asociada a varios proyectos de investigación financiados en VLSI y en sistemas integrados.