Physical Design and Mask Synthesis for Directed Self-Assembly Lithography

This book discusses physical design and mask synthesis of directed self-assembly lithography (DSAL). It covers the basic background of DSAL technology, physical design optimizations such as placement and redundant via insertion, and DSAL mask synthesis as well as its verification. Directed self-assembly lithography (DSAL) is a highly promising patterning solution in sub-7nm technology.

Introduces a highly promising patterning solution for next generation technology Provides a comprehensive overview of directed self-assembly lithography (DSAL) friendly physical design and DSAL-aware mask synthesis Written by leading developers of this technology

Autorentext

Seongbo Shim received B.S. and M.S. degrees in physics from Seoul National University, Korea, in 2004 and 2006 respectively, and a Ph.D. in electrical engineering from KAIST, Korea, in 2016. From 2006 to 2012, he was with the Semiconductor R&D Center, Samsung Electronics, where he was a Senior Engineer working on photolithography, computational lithography, optical proximity correction (OPC), and design for manufacturability (DFM) for advanced technologies. He has authored more than 40 papers on lithography, OPC, and DFM. He is the holder of 15 patents. His research interests include mask synthesis algorithms, VLSI CAD for the design-manufacturing interface, design technology co-optimization (DTCO) for emerging technologies, and machine learning for lithography optimizations.

Youngsoo Shin received B.S., M.S., and Ph.D. degrees in Electronics Engineering from Seoul National University, Korea. From 2001 to 2004, he was a Research Staff Member at the IBM T. J. Watson Research Center, Yorktown Heights, NY, USA. In 2004, he joined the Department of Electrical Engineering, KAIST, Korea, where he is currently a professor. He has served as a Program Chair of ICCD in 2014 and VLSI-SoC in 2015, and as a General Chair of ASP-DAC in 2018. He is an associate editor of IEEE Transactions on CAD and IEEE Design and Test. He is an IEEE Fellow.

Inhalt
Introduction.- DSAL Manufacturability.- Placement Optimization for DSAL.- Placement Optimization for MP-DSAL Compliant Layout.- Redundant Via Insertion for DSAL.