Power and Area Optimization in NoC by using Tailor Made Partitioning

NoC became a new paradigm to replace the SoC since the existing bus based system unable to accommodate the complexity of the SoC. A huge number of components were involved in the on-chip design. Each of these components needs to communicate with each other and carry their own function that will affect the scalability and the testability of the SoC in general. This project analyzes the main sources of power consumption in NoC based systems. Analytical power models of global interconnection links are studied at different levels of abstraction. Additionally, power measurement experiments are performed for different types of n-level network with related to die area of NoC.

Autorentext

Mohammad Irfan Abdul Rahman hat einen Bachelor in Elektrotechnik (Computer) von der Universiti Malaysia Sarawak (UNIMAS). Asrani Lit ist Forschungswissenschaftler am Fachbereich Elektrotechnik und Elektronik der UNIMAS. Fariza Mahyan ist Forschungswissenschaftlerin am Polytechnic of Kuching.