Power-Efficient High-Speed Parallel-Sampling ADCs for Broadband Multi-carrier Systems

This book addresses the challenges of designing high performance analog-to-digital converters (ADCs) based on the smart data converters concept, which implies context awareness, on-chip intelligence and adaptation. Readers will learn to exploit various information either a-priori or a-posteriori (obtained from devices, signals, applications or the ambient situations, etc.) for circuit and architecture optimization during the design phase or adaptation during operation, to enhance data converters performance, flexibility, robustness and power-efficiency. The authors focus on exploiting the a-priori knowledge of the system/application to develop enhancement techniques for ADCs, with particular emphasis on improving the power efficiency of high-speed and high-resolution ADCs for broadband multi-carrier systems.

Describes a signal/system-aware design approach for ADC design Presents a parallel-sampling architecture to exploit a-priori knowledge of the multi-carrier signal for enhancing power efficiency Includes two design examples in advanced CMOS technology for broadband multi-carrier systems, with discussions of the tradeoffs at various levels of the design Presents the IC implementation of an 11b 1GS/s parallel-sampling ADC in CMOS 65nm, showing state-of-the-art power efficiency Includes supplementary material: sn.pub/extras

Inhalt
Introduction.- Enhancing ADC performance by exploiting signal properties.- Parallel-sampling ADC architecture for mult-carrier signals.- Implementations of the parallel-sampling ADC architecture.- Conclusions and recommendations.