Power Grid Verification

Full-chip verication requires one to check if the power grid voltage drop does not exceed a certain threshold. The traditional simulation-based solution to this problem is computationally expensive, because of the large variety of possible circuit behaviors that would need to be simulated; it also has the disadvantage that it requires full knowledge of the details of the circuit attached to the grid, thereby precluding early verication of the grid. We propose a power grid verication technique that can be applied before the complete circuit has been designed and without exact knowledge of the circuit currents. We use current constraints, which are upper bound constraints on the currents that can be drawn from the grid, as a way to capture the uncertainty about the circuit details and activity. We propose one technique where we verify the worst case voltage as an optimization problem. Using this voltage verication and the constraints we also check the worst case delay of critical paths within the design. Lastly we implement a method of partitioning that allows us to verify grids of an industrial size within reasonable simulation times.

Autorentext

Denis has a PhD in electrical and computer engineering focused on EDA from the University of Toronto. His engineering career has spanned ATI/AMD, IBM Microelectronics and a few start-ups where he was responsible for managing the design of the companies' products.