Power Integrity Techniques in Nanometer VLSI Design

This book includes three major components in details: (1) Efficient algorithms to reduce the voltage noise of on-chip power grid networks without considering process variations in traditional VLSI design are discussed. The algorithms are based on the Sequence of Linear Programming (SLP) as the optimization engine and a scheme through circuit partitioning to handle large-sized million nodes of circuit analysis. (2) A statistical model order reduction technique called Statistical Spectrum Model Order Reduction (SSMOR) is proposed to address the variation of nanometer VLSI fabrication. The analysis is based on the Hermite polynomial chaos representation of random processes. (3) Moreover, a stochastic method is proposed to analyze the variation of voltage drop in on-chip power grid networks considering lognormal leakage current variations with spatial correlations. A novel noise reduction technique for power grid networks in VLSI design is proposed in the presence of variational leakage current sources. The optimization engines are based on both sensitivity-based conjugate gradient method and sequence of linear programming approach.

Autorentext

Dr. Jeffrey Fan is currently an Assistant Professor in electrical and computer engineering at Florida International University, U.S.A. Prior to his academic career, he held various senior technical positions at Western Digital, Emulex Corp., Adaptec, and Toshiba America in California, U.S.A. He is a Senior Member of IEEE.