Power Optimization in FPGA Routing circuits

The work optimizes power in 4T,5T,6T,7T,8T,9T and 10T SRAM by comparing their configurations. Two mode based operations are proposed : Mode I operation and Mode-II operation. A 10T based SRAM write driver circuitry is proposed and comparison of Static Power, Static Power Dissipation, Performance metrics like Power delay product and Energy delay product are compared using TANNER 7.0. In future , Adiabatic logic work circuitry has to be implemented and results are to be obtained.

Autorentext

Dr. Sundar Prakash Balaji erwarb seinen Doktortitel an der Anna University, Chennai. Er besitzt einen Bachelor- und einen Master-Abschluss der Anna-Universität, Chennai. Derzeit arbeitet er als außerordentlicher Professor am RVS Technical Campus - Coimbatore. Seine Interessen liegen in den Bereichen Low Power VLSI Design, ASIC Design und Solid State Devices.