Process representation and formalism

In the context of systems development life cycles (SDLC), a gap exists between the representations of the methodologies as processes on the one hand, for example using business process model and notation (BPMN), and the formalisms that would provide the level of analysability necessary to validate the corresponding processes on the other hand, for instance Petri nets. This doctoral thesis aims at bridging this gap by proposing a model in-between these two extremes that is simple yet expressive enough to be able to represent the processes, either directly or by translating BPMN diagrams to the model, while retaining enough formalism to allow its mapping to Petri nets, which then enables the execution of the diagrams but also opens the door to automatic or semi-automatic validation of some properties of the systems using well-known algorithms in graph theory or methods that are specific to Petri nets.

Autorentext

Dr. Eric Simon studied Computer Science at the University of Neuchâtel in Switzerland. He worked at CERN and for the Swiss Federal Administration, and obtained a Ph.D. degree at the same university, where he now occupies the positions of Quality Advisor and Lecturer.