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Processor and System-on-Chip Simulation
Details
This book reviews innovative technologies for simulation of computer architecture, presenting and discussing the principle technologies and current state of high-level hardware architecture simulation, both at the processor and the system-on-chip level.
Simulation of computer architectures has made rapid progress recently. The primary application areas are hardware/software performance estimation and optimization as well as functional and timing verification. Recent, innovative technologies such as retargetable simulator generation, dynamic binary translation, or sampling simulation have enabled widespread use of processor and system-on-chip (SoC) simulation tools in the semiconductor and embedded system industries. Simultaneously, processor and SoC simulation is still a very active research area, e.g. what amounts to higher simulation speed, flexibility, and accuracy/speed trade-offs. This book presents and discusses the principle technologies and state-of-the-art in high-level hardware architecture simulation, both at the processor and the system-on-chip level.
Presents state-of-the-art and future trends in processor and SoC simulation; Demonstrates how simulation helps to boost hardware and software design productivity; Addresses simulation requirements and technologies in the multicore context; Covers system aspects, such as virtual platforms, bus simulation, caches, power, design space exploration and a wide range of electronics industry segments. Includes supplementary material: sn.pub/extras
Klappentext
Processor and System-on-Chip Simulation Edited by: Rainer Leupers Olivier Temam The current trend from monolithic processors to multicore and multiprocessor systems on chips (MPSoC) with tens of cores and gigascale integration makes hardware architecture and software design more and more complex and costly. Therefore, simulation technology has become an extremely important pre-silicon verification and optimization vehicle. Simulation of computer architectures has made rapid progress recently. The primary application areas are hardware/software performance estimation and optimization, as well as functional and timing verification. Recent, innovative technologies, such as retargetable simulator generation, dynamic binary translation and sampling simulation have enabled widespread use of processor and system-on-chip (SoC) simulation tools in the semiconductor and embedded system industries. This book presents and discusses the principle technologies and state-of-the-art in high-level architecture software simulation, both at the processor and the system-on-chip level. • Presents state-of-the-art and future trends in processor and SoC simulation; • Demonstrates how simulation helps to boost hardware and software design productivity; • Addresses simulation requirements and technologies in the multicore context; • Covers system aspects, such as virtual platforms, bus simulation, caches, power, and design space exploration.
Inhalt
System Simulation and Exploration.- The Life Cycle of a Virtual Platform.- Full-System Simulation from Embedded to High-Performance Systems.- Toward the Datacenter: Scaling Simulation Up and Out.- Modular ISA-Independent Full-System Simulation.- Structural Simulation for Architecture Exploration.- Fast Simulation.- Accelerating Simulation with FPGAs.- Scalable Simulation for MPSoC Software and Architectures.- Adaptive High-Speed Processor Simulation.- Representative Sampling Using SimPoint.- Statistical Sampling.- Efficient Cache Modeling with Sparse Data.- Statistical Simulation.- Impact of Silicon Technology.- Memory Modeling with CACTI.- Thermal Modeling for Processors and Systems-on-Chip.- Rapid Technology-Aware Design Space Exploration for Embedded Heterogeneous Multiprocessors.- Embedded Systems Simulation.- IP Modeling and Verification.- Configurable, Extensible Processor System Simulation.- Simulation Acceleration in Wireless Baseband Processing.- Trace-Driven Workload Simulation for MPSoC Software Performance Estimation.
Weitere Informationen
- Allgemeine Informationen
- GTIN 09781489996077
- Genre Elektrotechnik
- Auflage 2010
- Editor Olivier Temam, Rainer Leupers
- Sprache Englisch
- Lesemotiv Verstehen
- Anzahl Seiten 360
- Größe H235mm x B155mm x T20mm
- Jahr 2014
- EAN 9781489996077
- Format Kartonierter Einband
- ISBN 1489996079
- Veröffentlichung 19.10.2014
- Titel Processor and System-on-Chip Simulation
- Gewicht 546g
- Herausgeber Springer US