Reconfigurable Networks-on-Chip

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This book provides a comprehensive survey of recent progress in the design and implementation of Networks-on-Chip. It addresses a wide spectrum of on-chip communication problems, ranging from physical, network, to application layers. Specific topics that are explored in detail include packet routing, resource arbitration, error control/correction, application mapping, and communication scheduling. Additionally, a novel bi-directional communication channel NoC (BiNoC) architecture is described, with detailed explanation. Written for practicing engineers in need of practical knowledge about the design and implementation of networks-on-chip; Includes tutorial-like details to introduce readers to a diverse range of NoC designs, as well as in-depth analysis for designers with NoC experience to explore advanced issues; Describes a variety of on-chip communication architectures, including a novel bi-directional communication channel NoC. From the Foreword:Overall this book shows important advances over the state of the art that will affect future system design as well as R&D in tools and methods for NoC design. It represents an important reference point for both designers and electronic design automation researchers and developers.--Giovanni De Micheli

Written for practicing engineers in need of practical knowledge about the design and implementation of networks-on-chip Includes tutorial-like details to introduce readers to a diverse range of NoC designs, as well as in-depth analysis for designers with NoC experience to explore advanced issues Describes a variety of on-chip communication architectures, including a novel bi-directional communication channel NoC Includes supplementary material: sn.pub/extras

Inhalt
Communication Centric Design.- Preliminaries.- Techniques for High Performance NoC Routing.- Performance-Energy tradeoffs for NoC Reliability.- Energy-aware Task Scheduling for NoC-based DVS System.- Bi-directional NoC Architecture.- Quality-of-Service in BiNoC.- Fault Tolerance in BiNoC.- Application Mapping for BiNoC.

Weitere Informationen

  • Allgemeine Informationen
    • GTIN 09781441993403
    • Genre Elektrotechnik
    • Auflage 2012
    • Sprache Englisch
    • Lesemotiv Verstehen
    • Anzahl Seiten 220
    • Größe H241mm x B160mm x T17mm
    • Jahr 2011
    • EAN 9781441993403
    • Format Fester Einband
    • ISBN 1441993401
    • Veröffentlichung 15.12.2011
    • Titel Reconfigurable Networks-on-Chip
    • Autor Sao-Jie Chen , Yu-Hen Hu , Wen-Chung Tsai , Ying-Cherng Lan
    • Gewicht 500g
    • Herausgeber Springer New York

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