Self-Sleep Circuits for Low Power VLSI Design

The present-day market has high demand for high functionality portable electronic devices whereas high performance chips are exceeding power dissipation limits. The feature size of the transistor came down drastically that power per unit area is more and demanding heat removal and cooling cost. Leakage Power is the prime factor in deep sub-micron designs. As the technology advances, leakage power dominates the switching power. This book emphasises the reduction of leakage power in standby mode using self-sleep circuits in distributed MTCMOS. The sizing and routing overheads in MTCMOS with sleep devices are reduced by using the self-sleep circuit. The effort is to target the challenges and design complexities related to sleep signal routing in distributed MTCMOS designs. The self-sleep circuit maintains good sleep signal integrity as it takes the well-defined clock signal of the chip as its only input. Self-sleep circuits are discussed which are incorporated in the designs of simple General Purpose Microprocessor and Fast Fourier Transform (FFT) Processor.

Autorentext

Dr. Esther Rani completed B.Tech from SK University. M.Tech and Ph.D from JNT University,India. She is currently Professor at CVR College of Engineering, Hyderabad. One of her patents is published by the Patent Office. She is Research Awardee for 3 years by the University Grants Commission, New Delhi. Completed a consultancy project for ECIL,India